PICs have many benefits, including miniaturisation, increased speed, reduced heat impacts, enormous capacity for integration, and compatibility with current processing processes that enable high yield, mass production, and lower costs.
FREMONT, CA: The integration of photonic components on a chip presents a number of difficulties from the viewpoint of traditional semiconductor makers. The need for photonic integrated circuits (also known as photonic chips or PICs) is expected to expand at an exponential rate in several business segments, including fibre optics for data communications and telecommunications.
The now well-known silicon complementary metal-oxide semiconductor (CMOS) manufacturing method was used in microelectronics to scale production to meet rising demand. The semiconductor industry prefers to create everything using CMOS technology because of its maturity. Numerous photonics items' quality was raised by the CMOS process's inherent complexity and maturity. The best examples are digital signal processors, which improve slow optics' performance and offer high-level encoding for current higher data rates. The range of technological platforms' ability to support the expansion of an integrated electronic device technology decreases as it becomes more complicated.
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In integrated photonics, a comparable pattern can be observed. To build the parts that make up a PIC, there are three main material platforms. A typical silicon wafer is used as the substrate in the fabrication of devices made of silicon, or silicon photonics (SiPh), and silicon nitride (SiN). Indium phosphide (InP), an III-V compound semiconductor material, is the other important material platform.
These three major platforms for integrating photonics work best together. On a PIC, no one platform can perform all functions. The main distinction between the platforms is that InP is the only one that permits the production of active components, such as lasers, in a photonic circuit. But when directing light signals, InP shows relatively extensive propagation losses, which makes it a poor material for passive parts like waveguides.
Complex electronics are generally relatively challenging to build, especially designs needing large-scale and very large-scale integration, which is a drawback of InP. Despite being more widely used as industrial materials, Si and SiN components cannot support lasing or other active elements. However, these materials, especially the SiN platform, have substantially lower light propagation losses and can potentially be used to guide the signals of single-photon emitters.
The InP platform's limited commercial availability in 3- and 4-in. wafer dimensions, as opposed to the approximately 12-in. diameter silicon-based platforms now accessible, is another point of differentiation. The economies of scale for high-volume, high-cost buildings constructed on InP substrates are impacted by this. The three material platforms are complementary, thus eventually the industry will strive to combine them most effectively to create incredibly complex PICs. The multiplicity of techniques to package photonic circuits multiplies the variety of material platforms that are available to PIC designers.
One of the initial methods used to develop silicon photonics was micropackaging. The process connects silicon platform waveguides to an external laser housed in a tiny container. However, as the number of lasers in a semiconductor design rises, the complexity of this technique multiplies substantially, posing problems for the platform's ability to scale. The approach used in hybrid integration is different. This method incorporates the entire PIC in an III-V material platform, including a laser, an array of lasers, or an array of lasers with modulators, as opposed to linking a silicon or SiN wafer to a laser. Companies engaged in photonics integration frequently use the broad phrase hybrid integration.
Another manufacturing method for using standard die bonding to attach III-V materials to the top of silicon is heterogeneous integration. This technology is rapidly developing. Although heterogeneous integration techniques are easily scaleable, they are expensive to create from scratch.
Another technology that has recently evolved is micro-transfer printing. It entails making coupons embedded with active devices and then scale-transferring them in relatively large volumes through a stamp so that several coupons can be transferred at the same time. Following alignment and bonding, the stamp is attached to a carrier wafer that has passive circuitry, such as silicon or SiN waveguides. Micropackaging is significantly less scalable than transfer printing. In the near future, it seems that many businesses will focus their resources on hybrid integration. Several unique PIC platforms, in addition to the three principal PIC material platforms of SiPh, SiN, and InP, give even more possibilities for the hybrid integration technique.
To accommodate the expanding number and diversity of integrated photonics applications, several material platforms will be required. The hybrid integration method of producing products is currently the most well-liked one in the sector. However, PICs that are entirely contained within layers of III-V materials that are formed on silicon using heteroepitaxy offer more functional, technological, and financial advantages. However, it will take more time for advancements to be made before heteroepitaxy can show operational photonic chips produced in large quantities. In the end, no one material platform can satisfy all of a PIC designer's requirements. The goal application will dictate the material platforms used in photonic chips, and the fabrication process will be based on production and cost constraints.
